2008Conference proceedings - Canadian Conference on Electrical and Computer EngineeringRequires access

New improved 1-bit full adder cells

Sreehari Veeramachaneni, M.B. Srinivas

Open publisher page 38 citations

Abstract

The 1-bit full adder is a very important component in the design of application specific integrated circuits. In this paper, authors propose three new 1-bit full adders having a delay of 2-transistor (2T) using existing XOR and XNOR gates. The power consumption, delay and area of these new full adders are compared with existing ones and the results appear to be promising. The combination of low power, low transistor count and lesser delay makes the new full adders a viable option for efficient design.

About this research paper

What this paper is about

The 1-bit full adder is a very important component in the design of application specific integrated circuits. In this paper, authors propose three new 1-bit full adders having a delay of 2-transistor (2T) using existing XOR and XNOR gates. The power consumption, delay and area of these new full adders are compared with existing ones and the results appear to be promising. The combination of low power, low transistor count and lesser delay makes the new full adders a viable option for efficient design.

Why it matters

OpenAlex reports 38 citations for this work. Citation counts describe recorded attention and do not establish research quality.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

The 1-bit full adder is a very important component in the design of application specific integrated circuits. In this paper, authors propose three new 1-bit full adders having a delay of 2-transistor (2T) using existing XOR and XNOR gates. The power consumption, delay and area of these new full adders are compared with existing ones and the results appear to be promising. The combination of low power, low transistor count and lesser delay makes the new full adders a viable option for efficient design.

Key concepts: Adder, XNOR gate, Serial binary adder, Transistor count, Computer science, Carry-save adder, Logic gate, Transistor

Related papers

Back to paper searchBrowse research topicsOriginal source
New improved 1-bit full adder cells — Research Paper | ScholarLens