Encoding of internal states in synthesis and implementation process of automata into FPGAs

The method of synthesis and implementation of Mealy FSMs into FPGAs is proposed. Synthesis is based on the architectural decomposition and multiple encoding of internal states. States are divided into subsets based on a current state and encoded separately in each subset. The state is decoded in the second-level circuit based on the multiple code and the code of a current state. It leads to implementation of FSM in double-level structure where utilization of both, LUTs and memory blocks of FPGA, is applied. It leads to balanced usage of hardware resources of an FPGA device.