K-band PLL based frequency synthesizer

The design and implementation of a K-band (22GHz) PLL frequency synthesizer is described. The frequency source was intended to be used in a test and measurement setup and the design goal was to achieve spurious free signal with lower phase noise and lesser harmonics. The PLL is locked at half of the output frequency; therefore there is frequency doubler at the output stage. The output signal from the PLL is multiplied, bandpass filtered and amplified to get the desired signal at desired power level.