A.W. Wieder, C. Werner, J. Harter
Abstract
An a priori model for CMOS design including latch-up prediction is presented. It is based on rigorous numerical 2-D simulations as well as on experimental data and gives accurate bulk-CMOS-scaling rules.
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An a priori model for CMOS design including latch-up prediction is presented. It is based on rigorous numerical 2-D simulations as well as on experimental data and gives accurate bulk-CMOS-scaling rules.
Key concepts: CMOS, Scaling, A priori and a posteriori, Semiconductor device modeling, Computer science, Electronic engineering, Integrated circuit design, Embedded system