High performance CMOS programmable logic array design

A high performance CMOS Programmable Logic Array (PLA) circuit implemented by a new circuit technique is presented. The gate outputs are preconditioned to minimize delay using a new clocking scheme and circuit design. A multi-level logic and layout synthesis tool which utilizes the CVTL circuit technique is also presented. We describe the overall design methodology for generating the high performance PLA. The simulated benchmark circuits show that the average power-delay product is 2.1 times smaller than the pseudo-nMOS implementations for 0.25 /spl mu/m process.