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Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications

Domenico Barretta, William Fornaciari, M. Sami, Dorian Bagni

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Abstract

Instruction level parallelism (ILP) extraction for multicluster VLIW processors is a very hard task. In this paper, we propose a retargetable architecture that can exploit ILP and thread level parallelism jointly, thus allowing an easier parallelism extraction and improving the performance with respect to traditional multicluster VLIW processors.

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What this paper is about

Instruction level parallelism (ILP) extraction for multicluster VLIW processors is a very hard task. In this paper, we propose a retargetable architecture that can exploit ILP and thread level parallelism jointly, thus allowing an easier parallelism extraction and improving the performance with respect to traditional multicluster VLIW processors.

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OpenAlex reports 6 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

Instruction level parallelism (ILP) extraction for multicluster VLIW processors is a very hard task. In this paper, we propose a retargetable architecture that can exploit ILP and thread level parallelism jointly, thus allowing an easier parallelism extraction and improving the performance with respect to traditional multicluster VLIW processors.

Key concepts: Very long instruction word, Computer science, Instruction-level parallelism, Parallel computing, Task parallelism, Thread (computing), Parallelism (grammar), Exploit

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