NoC datapath for polymorphic processors in embedded systems
Joshua Weber, Erdal Oruklu, Jafar Saniie
Abstract
Joshua Weber, Erdal Oruklu, Jafar Saniie
Abstract
Polymorphic processing has the goal of producing a processor combining the advantages of general purpose processing with the significant gains achievable by custom application specific computing. To achieve these ends a novel polymorphic processor architecture is presented. Incorporating networking on a chip (NoC) techniques into the datapath design has the potential to provide noticeable advantages when compared to a traditional processor datapath, especially for reconfigurable platforms such as FPGAs. This paper presents an architecture integrating NoC concepts into the design of a processor datapath in order to create a polymorphic processor. The paper will further explore and analyze the effect of topology choices and NoC design on the performance of polymorphic processors with specific focus on the impacts of NoC datapath integration.
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Polymorphic processing has the goal of producing a processor combining the advantages of general purpose processing with the significant gains achievable by custom application specific computing. To achieve these ends a novel polymorphic processor architecture is presented. Incorporating networking on a chip (NoC) techniques into the datapath design has the potential to provide noticeable advantages when compared to a traditional processor datapath, especially for reconfigurable platforms such as FPGAs. This paper presents an architecture integrating NoC concepts into the design of a processor datapath in order to create a polymorphic processor. The paper will further explore and analyze the effect of topology choices and NoC design on the performance of polymorphic processors with specific focus on the impacts of NoC datapath integration.
Key concepts: Datapath, Computer architecture, Computer science, Field-programmable gate array, Embedded system, Microarchitecture, Parallel computing, Reconfigurable computing