2002•1993 IEEE International Symposium on Circuits and SystemsRequires access
A two-pole circuit model for VLSI high-speed interconnection
Dian Zhou, Shun-Lin Su, Frank Tsui, Di Gao, J.S. Cong
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Abstract
A high-speed VLSI interconnection is modeled by using a generic distributed-RLC tree. Through a detailed analysis of the distributed-RLC tree a two-pole approximation system is established. Relating the solution of the two-pole approximation to the interconnection geometric parameters, a VLSI performance-driven layout problem is formulated which reveals the interplay between the interconnection performance and its geometrical parameters.>