Activity profile driven simultaneous vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designs

Leakage power (active and standby) is becoming increasingly dominant part of total power consumption in nano-scaled CMOS circuits. Present day commercial libraries provide multiple vt class cells to optimize active leakage power and circuit timing in functional/active mode, while techniques such as power gating have specifically addressed standby leakage reduction. However, the total leakage power which constitutes active and standby leakage components clearly depends on relative time spent in active and standby modes respectively which we refer to as activity profile of the design. Optimizing active and standby leakage independently without considering activity profile information can lead to sub-optimal leakage power savings. In this work, we propose activity profile driven optimization using multi-vt and power gating techniques where a trade-off between active and standby leakage components is performed to minimize the total leakage power. Results on benchmark circuits show that our technique achieves up to 3X improvement in leakage power savings on an average for long standby times while 2X-1.5X improvement for medium to low standby times as compared to conventional design techniques while preserving the original timing of the design.