A broadband, low phase noise, fast switching PLL frequency synthesizer

This paper presents a low phase noise, fast switching speed PLL synthesizer, which employs a simple and cost-effective direct-indirect architecture. The PLL residual noise floor of about -140 dBc/Hz is achieved by removing frequency division from the phase-locked loop, while the required frequency step is provided by multiplying and mixing the reference frequency. The measured phase noise at a 10 GHz output and 10 kHz offset is limited by the available reference at -120 dBc/Hz, while the tuning speed is less than 10 uSec.