Vhdl to fpga automatic ipcore generation: A case study on xilinx design flow

This paper aims at introducing a methodology that allows an easy implementation of IP-Cores focusing only on their functionalities rather than their interfaces and their inte-gration in a given architecture. The proposed approach im-plements all the communication infrastructure needed by a component, described in VHDL, to be finally inserted into a real architecture that can be implemented on FPGAs, re-ducing the time to market of the final implementation of the system. To validate the entire methodology, we have per-formed a comparison based on the CoreConnect communi-cation infrastructure, between our results with the classical Xilinx design flow using EDK and ISE. 1.