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A class of prefetch schemes for on-chip data caches

Anujan Varma, Gunjan Sinha

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Abstract

We introduce and evaluate a class of prefetch schemes for on-chip data caches in high-performance RISC processors. These schemes are conservative, initiating a prefetch only when a sequential pattern of references have been observed. Performance results based on traces of five programs in the SPEC suite on an IBM RS/6000 show that these schemes result in a significant reduction in miss ratio without the large increase in memory traffic associated with earlier schemes.

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What this paper is about

We introduce and evaluate a class of prefetch schemes for on-chip data caches in high-performance RISC processors. These schemes are conservative, initiating a prefetch only when a sequential pattern of references have been observed. Performance results based on traces of five programs in the SPEC suite on an IBM RS/6000 show that these schemes result in a significant reduction in miss ratio without the large increase in memory traffic associated with earlier schemes.

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OpenAlex reports 3 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

We introduce and evaluate a class of prefetch schemes for on-chip data caches in high-performance RISC processors. These schemes are conservative, initiating a prefetch only when a sequential pattern of references have been observed. Performance results based on traces of five programs in the SPEC suite on an IBM RS/6000 show that these schemes result in a significant reduction in miss ratio without the large increase in memory traffic associated with earlier schemes.

Key concepts: Instruction prefetch, Computer science, Parallel computing, Spec#, Suite, Class (philosophy), IBM, Cache

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