Complementary Schottky transistor logic

Abstract A high‐speed logic circuit, which is compatible on a single chip with I2L (integrated injection logic) and high‐voltage analog circuits is proposed. It is well known that the I2L features low power consumption and high packing density, but that its speed is lower than that of other bipolar circuits. On the other hand, high‐speed bipolar logic circuits consume a lot of power and occupy large area on a silicon chip. This paper proposes a new logic circuit which fills the gap in speed and density between the high‐speed bipolar and I2L circuits and reports the results of experiment. The new logic circuit uses a pnp transistor as a load device and a Schottky‐clamped npn transistor as a driver. An experimental circuit fabricated using an analog‐compatible technology showed a minimum delay time of 1.5 ns and a power‐delay product of 0.5 pJ. A counter circuit was operated at a frequency of 52 MHz.