2002•International Conference on Acoustics, Speech, and Signal ProcessingRequires access
The Motorola 16-bit DSP ASIC core
J.C. Lee, E. Cheval, Joseph Gergen
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Abstract
A 16-b user programmable CMOS general-purpose digital signal processing (DSP) application-specific IC (ASIC) core with customer-definable/customer-specific peripherals and input/output circuitry is described. The performance is 280 million operations per second (MOPS). The architecture is a 16-b version of the DSP56001 24-b architecture. The core consists of three processing units and an associated DSP instruction set. Also described is the first chip using this core, which has on-chip resources for optimal single-chip performance in medium-to-low speech rate encoding, digital communication, and high-speed control. The 16-b DSP ASIC core has been designed with silicon compiler tools to allow very fast integration of customer-defined on-chip peripherals or sigma-delta modulator blocks. Circuitry for on-chip emulation and test is described. A design methodology which allows customers to either design customer-specific peripherals or select peripherals from Motorola's DSP standard cell peripheral library is discussed.>