Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration

In this paper, a new adaptive PLL is implemented. This PLL employs a simple yet effective jitter test circuit to monitor the PLL jitter performance. Additionally, it uses a digital control unit to dynamically adjust the switched loop filter to suppress the jitter. By using this structure, the trade-off between the PLL locking speed and jitter performance can be balanced