Hot-Spot Detection and Correction Using Full-Chip-Based Process Window Analysis

In semiconductor industry, lithography technology has advanced with higher numerical aperture (NA) and/or lower-wavelength scanner on a yearly basis, which made it possible to keep shrinking the pattern size of semiconductor devices. Unfortunately, since chip size shrinking is currently limited to 193 nm ArF immersion scanners, lithographers have no further help from the equipment side for technology development. At this time, obtaining a compact design of a semiconductor device having a wide process window will be a key solution to realize the semiconductor industry's primary goal of fabricating high-density products with high yield. For a given particular design layout, the capability to analyze how difficult the process will be, which regions need to be modified to enlarge the process margin, and to provide guidelines to obtain a high-quality design are some of the key issues for the design for manufacturability (DfM). Many electronic design automation (EDA) companies are aggressively developing the method for DfM to meet the requirement for improved designs. In this paper, we discuss a method of full-chip-level lithography simulation using the optical proximity correction (OPC) engine and the calculation of process-limiting index parameters: mask error enhancement factor (MEEF), image log slope (ILS), and focus sensitivity (FS). Furthermore, this work includes a method of the quantitative rating of each design.