2002•Unpublished venueRequires access

Cost-effective implementation of ITU-T G.723.1 on a DSP chip

Sangmin Lee, Sangil Park, Yonngbeom Jang

Open publisher page 5 citations

Abstract

This paper presents a full-duplex, real-time implementation of ITU-T G.723.1 speech coder using the SSP1820, Samsung's DSP chip which is based on a 16-bit fixed-point Oak core. Optimization methods are proposed in order to reduce the total cycle time consumed in real-time implementation. The multi-pulse maximum likelihood quantization (MP-MLQ) excitation search block which is the most computation-intensive block in the coder is restructured to reduce the algorithmic redundancy. In addition, efficient filtering methods and memory management are utilized for further optimization. The bit-exact verification with the ITU test vectors and performance evaluation aspects are also discussed in this paper.

About this research paper

What this paper is about

This paper presents a full-duplex, real-time implementation of ITU-T G.723.1 speech coder using the SSP1820, Samsung's DSP chip which is based on a 16-bit fixed-point Oak core. Optimization methods are proposed in order to reduce the total cycle time consumed in real-time implementation. The multi-pulse maximum likelihood quantization (MP-MLQ) excitation search block which is the most computation-intensive block in the coder is restructured to reduce the algorithmic redundancy. In addition, efficient filtering methods and memory management are utilized for further optimization. The bit-exact verification with the ITU test vectors and performance evaluation aspects are also discussed in this paper.

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OpenAlex reports 5 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

This paper presents a full-duplex, real-time implementation of ITU-T G.723.1 speech coder using the SSP1820, Samsung's DSP chip which is based on a 16-bit fixed-point Oak core. Optimization methods are proposed in order to reduce the total cycle time consumed in real-time implementation. The multi-pulse maximum likelihood quantization (MP-MLQ) excitation search block which is the most computation-intensive block in the coder is restructured to reduce the algorithmic redundancy. In addition, efficient filtering methods and memory management are utilized for further optimization. The bit-exact verification with the ITU test vectors and performance evaluation aspects are also discussed in this paper.

Key concepts: Computer science, Digital signal processing, Redundancy (engineering), Quantization (signal processing), Block (permutation group theory), Embedded system, Computer hardware, Parallel computing

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