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A 12-bit vernier ring time-to-digital converter in 0.13μm CMOS technology

Jianjun Yu, Fa Foster Dai, Richard C. Jaeger

Open publisher page 62 citations

Abstract

A novel 12-bit Vernier ring time-to-digital converter (TDC) with 8ps of time resolution for digital-phase-locked-loop applications is presented. The TDC achieves a large detectable range of 32ns. The core of the TDC occupies 0.75 × 0.35 mm2 in a 0.13um CMOS technology. The total power consumption for the entire TDC chip is only 7.5mW with a 1.5V power supply at a sample rate of 15MSps.

About this research paper

What this paper is about

A novel 12-bit Vernier ring time-to-digital converter (TDC) with 8ps of time resolution for digital-phase-locked-loop applications is presented. The TDC achieves a large detectable range of 32ns. The core of the TDC occupies 0.75 × 0.35 mm2 in a 0.13um CMOS technology. The total power consumption for the entire TDC chip is only 7.5mW with a 1.5V power supply at a sample rate of 15MSps.

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OpenAlex reports 62 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

A novel 12-bit Vernier ring time-to-digital converter (TDC) with 8ps of time resolution for digital-phase-locked-loop applications is presented. The TDC achieves a large detectable range of 32ns. The core of the TDC occupies 0.75 × 0.35 mm2 in a 0.13um CMOS technology. The total power consumption for the entire TDC chip is only 7.5mW with a 1.5V power supply at a sample rate of 15MSps.

Key concepts: Vernier scale, CMOS, Time-to-digital converter, Electronic engineering, Chip, Phase-locked loop, Electrical engineering, Computer science

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