A Graph Based Processor Model for Retargetable Code Generation
J. Van Praet, D. Lanneer, J. Van, Praet D. Lanneer, G. Goossens, W. Geurts, H. De Man
Abstract
J. Van Praet, D. Lanneer, J. Van, Praet D. Lanneer, G. Goossens, W. Geurts, H. De Man
Abstract
Embedded processors in electronic systems typically are tuned to a few applications. Development of processor specific compilers is prohibitively expensive and as a result such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, we developed a retargetable and optimising code generator. It uses a graph based processor model that captures the connectivity, the parallelism and all architectural peculiarities of an embedded processor. In this paper, the processor model is presented and we formally define the code generation task, including code selection, register allocation and scheduling, in terms of this model. 1 Introduction Designers of electronic systems --- such as consumer electronics, communication systems and multi-media related products --- more and more incorporate programmable processors in their systems. Programmability offers them cost-effective hardware reuse and the flexibility to support last minute specification changes or to a...
OpenAlex reports 35 citations for this work. Citation counts describe recorded attention and do not establish research quality.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
Embedded processors in electronic systems typically are tuned to a few applications. Development of processor specific compilers is prohibitively expensive and as a result such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, we developed a retargetable and optimising code generator. It uses a graph based processor model that captures the connectivity, the parallelism and all architectural peculiarities of an embedded processor. In this paper, the processor model is presented and we formally define the code generation task, including code selection, register allocation and scheduling, in terms of this model. 1 Introduction Designers of electronic systems --- such as consumer electronics, communication systems and multi-media related products --- more and more incorporate programmable processors in their systems. Programmability offers them cost-effective hardware reuse and the flexibility to support last minute specification changes or to a...
Key concepts: Computer science, Code generation, Compiler, Parallel computing, Code (set theory), Register allocation, Scheduling (production processes), Graph