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A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs

Ping Lu, Pietro Andreani, Antonio Liscidini

Open publisher page 16 citations

Abstract

Two gated ring oscillators (GRO) act as the delay lines in an improved Vernier time-to-digital converter (TDC). The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS technology and achieves a resolution better than 5ps for a signal bandwidth of 800kHz. The current consumption is 3mA from 1.2V when operating at 25MHz.

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What this paper is about

Two gated ring oscillators (GRO) act as the delay lines in an improved Vernier time-to-digital converter (TDC). The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS technology and achieves a resolution better than 5ps for a signal bandwidth of 800kHz. The current consumption is 3mA from 1.2V when operating at 25MHz.

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Available abstract

Two gated ring oscillators (GRO) act as the delay lines in an improved Vernier time-to-digital converter (TDC). The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS technology and achieves a resolution better than 5ps for a signal bandwidth of 800kHz. The current consumption is 3mA from 1.2V when operating at 25MHz.

Key concepts: Vernier scale, Time-to-digital converter, CMOS, Ring oscillator, Electronic engineering, Computer science, Quantization (signal processing), Jitter

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A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs — Research Paper | ScholarLens