Simulating the behavior of software modules by trace rewriting
Yabo Wang, David Lorge Parnas
Abstract
Yabo Wang, David Lorge Parnas
Abstract
The trace assertion method is a module interface specification method based on the finite state machine model. To support this method, we plan to develop a specification simulation tool, a trace simulator, that symbolically interprets trace assertions of trace specifications and simulates the externally observable behavior of the modules specified. We first present the trace assertion method. Then we formally define trace rewriting systems and show how trace rewriting, a technique similar to term rewriting, can be applied to implement trace simulation.>
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The trace assertion method is a module interface specification method based on the finite state machine model. To support this method, we plan to develop a specification simulation tool, a trace simulator, that symbolically interprets trace assertions of trace specifications and simulates the externally observable behavior of the modules specified. We first present the trace assertion method. Then we formally define trace rewriting systems and show how trace rewriting, a technique similar to term rewriting, can be applied to implement trace simulation.>
Key concepts: TRACE (psycholinguistics), Rewriting, Computer science, Assertion, Programming language, Term (time), Theoretical computer science, Philosophy