A genetic approach to test application time reduction for full scan and partial scan circuits

Full scan and partial scan are effective design-for-testability techniques for achieving high fault coverage. However, test application time can be high if long scan chains are used. Reductions in test application time can be made if flip-flop values are not scanned in and out before and after every test vector is applied. Previous research has used deterministic fault-oriented combinational and sequential circuit test generators in generating test vectors and sequences and in deciding when to scan the flip-flops. In this work we use genetic algorithms to generate compact test sets which limit the scan operations. Results for the ISCAS89 sequential benchmark circuits show that significant reductions in test application time can be achieved, especially for partial scan circuits.