SDG vs ADG with tied and independent gate options in the subthreshold logic for ultra low power applications

Subthreshold region of operation has gained wide research interest for applications requiring Ultra low power consumption and medium frequency of operation. Double gate MOSFETs are proved to be better candidates for subthreshold operation due to their near ideal subthreshold slope and negligible gate capacitance. However it is not yet clear whether symmetric (SDG) or Asymmetric (ADG) DG with options of Tied (3T) and Independent gates (4T) are optimal for subthreshold circuit design. In this paper, we compare the performance characteristics of SDG and ADG circuits with tied (3T) and Independent gate (4T) options for the subthreshold logic by applying them to some basic logic gates such as NAND, NOR gates for the 32 nm technology node. We also present the performance comparisons of SDG and ADG circuits for subthreshold logic in the presence of supply voltage and temperature variations. We found that 3T ADG circuits offer approximately 13-14% better power consumption, 4-5% better speed and 16-18.3% better PDP than 3TSDG based circuits.