Generating ASIC test vectors with Verilog

Compiling a design verification test suite is a non-trivial task. Creating that test suite to satisfy an ASIC vendor can be even more difficult. An awareness of existing Verilog HDL capabilities may assist design engineers in the creation of ASIC test vectors to satisfy ASIC-vendor vector requirements. This paper outlines simple Verilog techniques which demonstrate Verilog's power not only for describing hardware, but for creating ASIC test vectors.>