Synthesis flow for designing a high performance microprocessor

This paper describes the methodology for the automated synthesis flow used for a high-performance microprocessor project at Intel. The flow presents a standard method of automatically translating the RTL description of the microprocessor to placed and routed gates. The flow optimizes the design for timing and power, while ensuring that the final netlist is logically equivalent to the RTL and that all of the backend checks and rules are satisfied (for example noise, many electrical rules, routing rules, metal reliability, and so forth). The typical inputs to the flow are RTL, timing constraints and floorplan description, while the typical outputs are a netlist and layout. The netlist and layout are used as inputs to the other tools for logical and physical verification of the design.