EFFICIENT SNUBBER CIRCUIT FOR HIGH VOLTAGE THREE-LEVEL GTO INVERTERS

A new low loss snubber circuit including overvoltage clamping circuit for three-level GTO inverter is presented. The proposed snubber circuit is effective in the restriction of the dv/dt and the overvoltage values across each GTO at turn-off and the snubber loss is less than the half that of the conventional RCD snubber circuit. In addition, there is no blocking voltage balancing problem between the inner and the outer GTOs that occurs in the case that conventional RCD snubber circuit is used in three-level inverter topology. Experimental results demonstrate that the proposed snubber circuit is very effective for a large capacity three-level GTO inverter.