Effective Instruction Fetch Stage Design for 16-Bit Instruction Set Architecture

The 16-bit instruction set architecture has merits in terms of code size reduction and instruction cache efficiency. But we have taken the advantages at the cost of performance due to lack of an available expression space for a long immediate value, a three-address mode and so on. This paper presents a new instruction coalescing technique named as move folding to remove redundant move instructions caused by the limitation of the 16-bit instruction set.We prove effectiveness of the technique by implementing it on a commercial microprocessor. The proposed move folding technique improves speedup of 5% on average and up to 18% at the cost of 4.3% hardware complexity increment.