Low Offset, High PSRR, CMOS Bandgap Voltage Reference
Yong-Rui Zhao, Lai Xinquan
Abstract
Yong-Rui Zhao, Lai Xinquan
Abstract
A CMOS Bandgap Voltage Reference (BVR) with the characteristics of low offset and high power-supply rejection ratio (PSRR) is presented. In order to reduce the effect of offset of operation amplifier (OPA), the voltage difference of base-emitter junctions of substrate bipolar transistors is maximized; meanwhile the factor of offset voltage could be minimized. The feedback loop constructed by proportional to absolute temperature (PTAT) current source and an OPA is employed to improve the PSRR. The circuit was designed and simulated in a standard 0.35-μm CMOS process, with a power supply of 3 volt. The relative accuracy is increased by 5 times compared with conventional circuit. PSRR of the circuit is ~108dB at low-frequency. Furthermore, temperature coefficient (TC) of 17ppm/℃ over a wide temperature range of -40~115℃.The whole circuit including the OPA draws only 22 A from supply voltage. Silicon area is 0.037mm2. Streszczenie. Opisano pasmowy wzorzec napiecia w technologii CMOS charakteryzujący sie malym pelzaniem zera i duzym wspolczynnikiem usuwania skladowej zasilającej. Uklad zaprojektowano w technologii 0.35m z napieciem zasilania 3V. (Pasmowy wzorzec napiecia z malym pelzaniem zera i duzym wspolczynnikiem PSRR)
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A CMOS Bandgap Voltage Reference (BVR) with the characteristics of low offset and high power-supply rejection ratio (PSRR) is presented. In order to reduce the effect of offset of operation amplifier (OPA), the voltage difference of base-emitter junctions of substrate bipolar transistors is maximized; meanwhile the factor of offset voltage could be minimized. The feedback loop constructed by proportional to absolute temperature (PTAT) current source and an OPA is employed to improve the PSRR. The circuit was designed and simulated in a standard 0.35-μm CMOS process, with a power supply of 3 volt. The relative accuracy is increased by 5 times compared with conventional circuit. PSRR of the circuit is ~108dB at low-frequency. Furthermore, temperature coefficient (TC) of 17ppm/℃ over a wide temperature range of -40~115℃.The whole circuit including the OPA draws only 22 A from supply voltage. Silicon area is 0.037mm2. Streszczenie. Opisano pasmowy wzorzec napiecia w technologii CMOS charakteryzujący sie malym pelzaniem zera i duzym wspolczynnikiem usuwania skladowej zasilającej. Uklad zaprojektowano w technologii 0.35m z napieciem zasilania 3V. (Pasmowy wzorzec napiecia z malym pelzaniem zera i duzym wspolczynnikiem PSRR)
Key concepts: Power supply rejection ratio, Bandgap voltage reference, Input offset voltage, CMOS, Electrical engineering, Materials science, Offset (computer science), Voltage reference