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2011•Unpublished venueRequires access

The RF receiver front-end chip design with the transformer balun for DSRC applications

Jhin‐Fang Huang, Yong-Jhen Jiangn, Ron‐Yi Liu

Open publisher page 3 citations

Abstract

A 0.18 μm CMOS RF receiver front-end applying in DSRC systems is presented in this paper. The proposed receiver front-end includes the current-reused LNA, the folded Giber cell mixer, and the Colpitts VCO. Also, this paper presents the design methodology and application of the transformer balun for RFIC. The measured results of the proposed receiver front-end show the input return loss of 30.5 dB, the conversion gain of 17.5 dB, the (DSB) NF of 4.2 dB, and the third-order intercept point (IIP3) of -10 dBm at 5.8 GHz frequency. The chip area of the proposed receiver front-end including pads is 1.4 × 1.4 mm with the total power dissipation of 49.78 mW.

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What this paper is about

A 0.18 μm CMOS RF receiver front-end applying in DSRC systems is presented in this paper. The proposed receiver front-end includes the current-reused LNA, the folded Giber cell mixer, and the Colpitts VCO. Also, this paper presents the design methodology and application of the transformer balun for RFIC. The measured results of the proposed receiver front-end show the input return loss of 30.5 dB, the conversion gain of 17.5 dB, the (DSB) NF of 4.2 dB, and the third-order intercept point (IIP3) of -10 dBm at 5.8 GHz frequency. The chip area of the proposed receiver front-end including pads is 1.4 × 1.4 mm with the total power dissipation of 49.78 mW.

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Available abstract

A 0.18 μm CMOS RF receiver front-end applying in DSRC systems is presented in this paper. The proposed receiver front-end includes the current-reused LNA, the folded Giber cell mixer, and the Colpitts VCO. Also, this paper presents the design methodology and application of the transformer balun for RFIC. The measured results of the proposed receiver front-end show the input return loss of 30.5 dB, the conversion gain of 17.5 dB, the (DSB) NF of 4.2 dB, and the third-order intercept point (IIP3) of -10 dBm at 5.8 GHz frequency. The chip area of the proposed receiver front-end including pads is 1.4 × 1.4 mm with the total power dissipation of 49.78 mW.

Key concepts: Balun, RF front end, Superheterodyne receiver, CMOS, Electrical engineering, RFIC, Transformer, Noise figure

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