2006•Unpublished venueRequires access
A Low-Phase-Noise Area-Efficient 3-D LC VCO in Standard 0.18-um CMOS Technology
Hsiao‐Chin Chen, Tao Wang, Shey‐Shi Lu, Guo-Wei Huang
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Abstract
A miniaturized (0.224 mm2) 4.5~5.0 GHz 3-D LC VCO possessing area-efficient metal-6 on-chip inductors is implemented in 0.18 um 1P6M CMOS technology. With inductors directly above the other devices, this VCO shows a measured phase noise of -124.6 dBc/Hz at 1 MHz offset from the 4.9 GHz carrier while dissipating 24 mW. The figure-of-merit (-184.7 dBc/Hz) achieved is better than most of the previous state-of-art results of the CMOS LC VCOs while occupying only half the die area