2002Unpublished venueRequires access

Electrical characterization of quad flat non-lead package for RFIC applications

Nansen Chen, Kevin Chiang, T.D. Her, Yeong-Lin Lai, Chichyang Chen

Open publisher page 6 citations

Abstract

The QFN package is a near chip scale package plastic encapsulated package with a coppery leadframe substrate. The purpose of this paper was to establish the wideband equivalent circuit model of QFN packages for RF applications. Only short-path configuration was required for S-parameter measurement to achieve this purpose. The comparison of S11 and S21 between S-parameter measurement and optimized equivalent circuit model verified that those results were well matched and optimized. The parasitic parameters of equivalent circuit were reliable up to 6 GHz. The methods proposed in this paper may reduce the cost for samples preparation and chip simulation run time.

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What this paper is about

The QFN package is a near chip scale package plastic encapsulated package with a coppery leadframe substrate. The purpose of this paper was to establish the wideband equivalent circuit model of QFN packages for RF applications. Only short-path configuration was required for S-parameter measurement to achieve this purpose. The comparison of S11 and S21 between S-parameter measurement and optimized equivalent circuit model verified that those results were well matched and optimized. The parasitic parameters of equivalent circuit were reliable up to 6 GHz. The methods proposed in this paper may reduce the cost for samples preparation and chip simulation run time.

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OpenAlex reports 6 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

The QFN package is a near chip scale package plastic encapsulated package with a coppery leadframe substrate. The purpose of this paper was to establish the wideband equivalent circuit model of QFN packages for RF applications. Only short-path configuration was required for S-parameter measurement to achieve this purpose. The comparison of S11 and S21 between S-parameter measurement and optimized equivalent circuit model verified that those results were well matched and optimized. The parasitic parameters of equivalent circuit were reliable up to 6 GHz. The methods proposed in this paper may reduce the cost for samples preparation and chip simulation run time.

Key concepts: Quad Flat No-leads package, RFIC, Chip-scale package, Equivalent circuit, Integrated circuit packaging, Electronic engineering, Chip, Computer science

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