1992•Unpublished venueOpen access

A boundary scan test controller for hierarchical BIST

J.S. Matos, F.S. Pinto, José Manuel Martins Ferreira

Abstract

A test controller for BIST of Boundary Scan Boards is described. It consists of a test processor core, with an optimized architecture for controlling the board-level BST infrastructure, and a system level testability bus interjace, allowing the implementation of a hierarchical test strategy. Automatic test pattern generation for this dedicated processor simplifies the task of providing a board-level BIST solution.

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Available abstract

Key concepts: Boundary scan, Built-in self-test, Testability, Design for testing, Embedded system, Computer science, Controller (irrigation), Automatic test pattern generation