Multilevel monolithic 3D inductors on silicon
Juho Son, Sun-Hong Kim, Seok-Woo Choi, DoHwan Rho, D.Y. Kim
Abstract
Juho Son, Sun-Hong Kim, Seok-Woo Choi, DoHwan Rho, D.Y. Kim
Abstract
This paper has been the analysis of passive devices in Si RF and microwave. Multilevel monolithic 3D inductors implemented in a standard CMOS technology are presented. Since on-chip inductors are constrained to be planar, the typical solution is to form a spiral. Proposed inductors are composed of 3D structures requiring no extra processing steps. Inductances are higher in increasing the mutual inductance besides the self-inductance. In this reason, this structure gives rise to a quality factor Q and a inductance using 3D geometry in small areas.
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This paper has been the analysis of passive devices in Si RF and microwave. Multilevel monolithic 3D inductors implemented in a standard CMOS technology are presented. Since on-chip inductors are constrained to be planar, the typical solution is to form a spiral. Proposed inductors are composed of 3D structures requiring no extra processing steps. Inductances are higher in increasing the mutual inductance besides the self-inductance. In this reason, this structure gives rise to a quality factor Q and a inductance using 3D geometry in small areas.
Key concepts: Inductor, Inductance, CMOS, Q factor, Equivalent series inductance, Microwave, Electronic engineering, Planar