1996•European Design Automation ConferenceRequires access

Synthesis from mixed specifications

Giovanni De Micheli, Vincent J. Mooney, C. Coelho, Toshiyuki Sakamoto

Abstract

We present a hardware synthesis system that accepts system-level specifications in both Verilog HDL and C. A synchronous semantics is assumed for both languages in order to guarantee a uniform underlying model. The rationale for mixed input specifications is to support hardware/software co-design by allowing the migration to hardware of system modules originally described in the C language. We discuss assumptions and limitations of the input description style, a high-level synthesis system, and the application of such a system to some design examples.

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Key concepts: Computer science, Verilog, Hardware description language, Programming language, High-level synthesis, Semantics (computer science), Software, Electronic system-level design and verification