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Transplant and Optimization of H.264 Encoder Based on DSP Platform

Shi Zhang, Xiaozhi Liu, Tianguang Jiao, Jinlong Qi

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Abstract

Compared with other previous standards, H.264 standard has achieved great improvement in aspects of hierarchical intra/inter prediction coding, multi-frame reference, prediction accuracy. It's practical and necessary that the optimization and implementation of H.264 baseline profile encoder on the platform of TMS320DM642. Based on the architectural features of DSP and the computational complexity analysis of H.264 encoder, the H.264 encoder has been optimized from the following three aspects: algorithm, data transfer and memory/Cache use. The experimental results demonstrate that the optimized H.264 encoder can achieve the encoding speed of more than 24 frames per second for the video sequences with CIF format, which can meet the real-time requirements of the applications.

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What this paper is about

Compared with other previous standards, H.264 standard has achieved great improvement in aspects of hierarchical intra/inter prediction coding, multi-frame reference, prediction accuracy. It's practical and necessary that the optimization and implementation of H.264 baseline profile encoder on the platform of TMS320DM642. Based on the architectural features of DSP and the computational complexity analysis of H.264 encoder, the H.264 encoder has been optimized from the following three aspects: algorithm, data transfer and memory/Cache use. The experimental results demonstrate that the optimized H.264 encoder can achieve the encoding speed of more than 24 frames per second for the video sequences with CIF format, which can meet the real-time requirements of the applications.

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Available abstract

Compared with other previous standards, H.264 standard has achieved great improvement in aspects of hierarchical intra/inter prediction coding, multi-frame reference, prediction accuracy. It's practical and necessary that the optimization and implementation of H.264 baseline profile encoder on the platform of TMS320DM642. Based on the architectural features of DSP and the computational complexity analysis of H.264 encoder, the H.264 encoder has been optimized from the following three aspects: algorithm, data transfer and memory/Cache use. The experimental results demonstrate that the optimized H.264 encoder can achieve the encoding speed of more than 24 frames per second for the video sequences with CIF format, which can meet the real-time requirements of the applications.

Key concepts: Encoder, Computer science, Digital signal processing, Coding (social sciences), Encoding (memory), Cache, Frame (networking), Computer hardware

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