A New Solution to Implement Multi-Full-Scan-Chain Test with JTAG

This paper presents a DFT (design for test) solution which combines boundary-scan and full-scan together in SoC testability design. Using this method, full scan test and boundary scan test can be easily performed just through the common IEEE 1149.1 (JTAG) access interface. Our final goal is not only to implement fewer test-pin-count, but rather to provide an IEEE 1149.1 compatible architecture to achieve the unified boundary scan test and multi-full-scan-chain test. To do this, a new instruction "SCAN" is added in JTAG instruction register, at the same time, a few kinds of modified boundary scan cells and minor modifications to the TAP controller are adopted