Aliasing-free signature analysis for RAM BIST
V. N. Yarmolik, M. Nicolaidis, O. Kebichi
Abstract
V. N. Yarmolik, M. Nicolaidis, O. Kebichi
Abstract
Signature analyzers are very efficient output response compactors in BIST techniques. The only limitation of signature analysis is the fault coverage reduction (aliasing) due to the information loss inherent to any data compaction. In this paper, in order to increase the effectiveness of RAM BIST, we fake advantage from the regularity of the RAM test algorithms and we show that aliasing-free signature analysis can be achieved in RAM BIST.
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Signature analyzers are very efficient output response compactors in BIST techniques. The only limitation of signature analysis is the fault coverage reduction (aliasing) due to the information loss inherent to any data compaction. In this paper, in order to increase the effectiveness of RAM BIST, we fake advantage from the regularity of the RAM test algorithms and we show that aliasing-free signature analysis can be achieved in RAM BIST.
Key concepts: Signature (topology), Aliasing, Built-in self-test, Computer science, Linear feedback shift register, Reduction (mathematics), Computer hardware, Embedded system