Balancing the tradeoffs between coefficient quantization and internal quantization in FIR digital filters

To implement digital FIR filters in hardware such as ASICs, FPGAs and custom VLSI, decisions regarding input quantization, coefficient quantization and internal rounding are required. This paper investigates the relationship between coefficient quantization and internal rounding, as well as how these two sources of quantization error can be used to achieve better designs for implementation. Our analysis indicates that internal results can be rounded to approximately the same number of bits used for coefficient quantization without much increase in quantization error if the original input is assumed to be finite precision. This result indicates that chip area can be reduced in many implementations.