Low cost clock cleaner solution for reference clock sources

With the increase in data processing speeds, the requirement for a clean reference clock source for high-speed data processing is paramount. A clean reference clock source for a high-speed data system must satisfy the following criteria: generates a clock signal with very fast rising and falling edges, exhibits low intrinsic jitter and does not add additional jitters through the clock distribution network. Generally, the cost of a reference clock source rises with the quality of the clock signal. This paper proposes a low-cost clock cleaner solution for reference clock sources called the Clock Cleaner. The Clock Cleaner provides a wide range of reference clock frequencies with very low phase noise and jitter. The Clock Cleaner offers an affordable and flexible way for electronic system designers to prototype their high-speed applications. This paper presents the implementation of the Clock Cleaner using an Altera Cyclone III FPGA device and a NIOS II processor. This paper also analyzes the Clock Cleaner's phase noise and jitter performance and compares them with two commercial clock generation equipments.