Implementation of High Throughput Radix-16 FFT Processor

The extension of radix-4 algorithm to radix-16 to achieve the high throughput of 2.59 giga- samples/s for WPAN's.We are also reformulating radix-16 algorithm to achieve low-complexity and low area cost and high performance. Radix -16 FFT is obtained by cascaded the radix -4 butterfly units. It facilitates low-complexity realization of radix-16 butterfly operation and high operation speed due to its optimized pipelined structure. Besides, a new three-stage multiplier for twiddle factor multiplication is also proposed, which has lower area and power consumption than conventional complex multipliers. Equipped with those new performance-boosting techniques, overall the proposed radix-16 FFT processor is area-efficient with high data processing rate and hardware utilization efficiency. The control circuit of the proposed simplified radix-24 FFT SDF architecture is simpler than that of the direct radix-16 FFT SDF structure. The multiplier cost of the proposed FFT architecture is less than that of the previous FFT structures in 256-point FFT applications. The throughput of the proposed FFT processor is one sample per clock. Although the radix-16 FFT algorithm has Less computational complexity, the control circuit of the direct radix-16 SDF architecture for implementing radix-16 FFT is very complex. Thus, the efficient simplified radix-24 SDF structure, which is described in the next section, will be applied to radix-16 FFT algorithm.