Harmonic Performance Evaluation of CMOS SOI SPDT Switch with Embedded Lateral Substrate Model

This paper describes a single pole, double throw (SPDT) CMOS SOI switch in 180nm Technology developed for the GSM 900MHz RF switch applications. Silicon-on-Insulator (SOI) CMOS FETs have many properties which are desirable for RF switch applications. By being manufactured on an insulator substrate, the bulk parasitic capacitances typical of CMOS FETs are eliminated. The SOI FET has a very low Ron-Coff product, allowing for low insertion loss and high isolation in high frequency applications. Despite the low breakdown voltage intrinsic to Si, SOI FETs can be stacked in series to withstand high voltages. This work discuss Harmonic Performance and Power handling behavior of SOI CMOS Switch with non-linear lateral substrate model as a function of gate and body biasing voltages.