Roger Espasa, Mateo Valero
Abstract
Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to executing 15 to 26 scalar instructions/cycle for numerical applications.
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Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to executing 15 to 26 scalar instructions/cycle for numerical applications.
Key concepts: Computer science, Instruction-level parallelism, Parallel computing, Data parallelism, Parallelism (grammar), Task parallelism, Instruction set, Computer architecture