1998•IEEE Transactions on Consumer ElectronicsRequires access

A new PLL frequency synthesizer using multi-programmable divider

Y. Sumi, Kouichi Syoubu, Shigeki Obote, Y. Fukui, Yasushi Itoh

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Abstract

In this paper, we propose a new phase locked loop (PLL) frequency synthesizer utilizing the multiprogrammable divider which can attain a higher speed lock-up time by increasing the loop gain. The effectiveness of the PLL frequency synthesizer with the multiprogrammable divider are shown by theoretical considerations and experimental results.

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What this paper is about

In this paper, we propose a new phase locked loop (PLL) frequency synthesizer utilizing the multiprogrammable divider which can attain a higher speed lock-up time by increasing the loop gain. The effectiveness of the PLL frequency synthesizer with the multiprogrammable divider are shown by theoretical considerations and experimental results.

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OpenAlex reports 8 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

In this paper, we propose a new phase locked loop (PLL) frequency synthesizer utilizing the multiprogrammable divider which can attain a higher speed lock-up time by increasing the loop gain. The effectiveness of the PLL frequency synthesizer with the multiprogrammable divider are shown by theoretical considerations and experimental results.

Key concepts: Phase-locked loop, Frequency synthesizer, PLL multibit, Frequency divider, Frequency multiplier, Electronic engineering, Direct digital synthesizer, Current divider

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