A new PLL frequency synthesizer using multi-programmable divider
Y. Sumi, Kouichi Syoubu, Shigeki Obote, Y. Fukui, Yasushi Itoh
Abstract
Y. Sumi, Kouichi Syoubu, Shigeki Obote, Y. Fukui, Yasushi Itoh
Abstract
In this paper, we propose a new phase locked loop (PLL) frequency synthesizer utilizing the multiprogrammable divider which can attain a higher speed lock-up time by increasing the loop gain. The effectiveness of the PLL frequency synthesizer with the multiprogrammable divider are shown by theoretical considerations and experimental results.
OpenAlex reports 8 citations for this work. Citation counts describe recorded attention and do not establish research quality.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
In this paper, we propose a new phase locked loop (PLL) frequency synthesizer utilizing the multiprogrammable divider which can attain a higher speed lock-up time by increasing the loop gain. The effectiveness of the PLL frequency synthesizer with the multiprogrammable divider are shown by theoretical considerations and experimental results.
Key concepts: Phase-locked loop, Frequency synthesizer, PLL multibit, Frequency divider, Frequency multiplier, Electronic engineering, Direct digital synthesizer, Current divider