High speed parallel-prefix modulo 2/sup n/+1 adders for diminished-one operands

We present a new methodology for designing modulo 2/sup n/+1 adders with operands in the diminished-one number system. The proposed methodology leads to parallel-prefix adder implementations. Both an analytical model and VLSI implementations in a standard-cell technology are utilized for comparing the adders designed following the proposed methodology against the existing solutions. Our results indicate; that the proposed parallel-prefix adders are considerably faster than any other already known in the open literature and as fast as the corresponding modulo 2/sup n/ and modulo 2/sup n/-1 adders.