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Design of enhanced differential cascode voltage switch logic (EDCVSL) circuits for high fan-in gate

Dae Woon Kang, Yong-Bin Kim

Open publisher page 18 citations

Abstract

In this paper, a new logic-style, enhanced differential cascode voltage switch logic (EDCVSL), is presented for high performance and low power VLSI. EDCVSL simplifies the logic tree of DCVSL, and dramatically reduces the number of interconnects by eliminating the complementary inputs, while maintaining the features of DCVSL. Simulation results of EDCVSL show less power consumption compared to the traditional DCVSL architecture, while EDCVSL keeps DCVSL's advantages.

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What this paper is about

In this paper, a new logic-style, enhanced differential cascode voltage switch logic (EDCVSL), is presented for high performance and low power VLSI. EDCVSL simplifies the logic tree of DCVSL, and dramatically reduces the number of interconnects by eliminating the complementary inputs, while maintaining the features of DCVSL. Simulation results of EDCVSL show less power consumption compared to the traditional DCVSL architecture, while EDCVSL keeps DCVSL's advantages.

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OpenAlex reports 18 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

In this paper, a new logic-style, enhanced differential cascode voltage switch logic (EDCVSL), is presented for high performance and low power VLSI. EDCVSL simplifies the logic tree of DCVSL, and dramatically reduces the number of interconnects by eliminating the complementary inputs, while maintaining the features of DCVSL. Simulation results of EDCVSL show less power consumption compared to the traditional DCVSL architecture, while EDCVSL keeps DCVSL's advantages.

Key concepts: Cascode, Pass transistor logic, Logic level, Logic family, Logic gate, Resistor–transistor logic, Diode–transistor logic, Emitter-coupled logic

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