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2002•Unpublished venueRequires access

Design of high performance two stage CMOS cascode op-amps with stable biasing

Pradip Mandal, V. Visvanathan

Open publisher page 3 citations

Abstract

The technique of mirror biasing is introduced and applied to a very high gain two stage CMOS cascode op-amp, in order to desensitize its output voltage to bias variations. Various performance metrics like low frequency common mode and power supply rejection ratios, slew rate and the sensitivity of the systematic offset are substantially improved. The improved performance is theoretically predicted and substantiated through circuit simulations.

About this research paper

What this paper is about

The technique of mirror biasing is introduced and applied to a very high gain two stage CMOS cascode op-amp, in order to desensitize its output voltage to bias variations. Various performance metrics like low frequency common mode and power supply rejection ratios, slew rate and the sensitivity of the systematic offset are substantially improved. The improved performance is theoretically predicted and substantiated through circuit simulations.

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OpenAlex reports 3 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Method / approach

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Available abstract

The technique of mirror biasing is introduced and applied to a very high gain two stage CMOS cascode op-amp, in order to desensitize its output voltage to bias variations. Various performance metrics like low frequency common mode and power supply rejection ratios, slew rate and the sensitivity of the systematic offset are substantially improved. The improved performance is theoretically predicted and substantiated through circuit simulations.

Key concepts: Cascode, Slew rate, Biasing, CMOS, Offset (computer science), Operational amplifier, Electronic engineering, Voltage

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