Algorithms for address assignment in DSP code generation

Abstract { This paper presents DSP code optimization techniques, which originate from dedicated memory address generation hardware. We de ne a generic model of DSP address generation units. Based on this model, we present e cient heuristics for computing memory layouts for program variables, which optimize utilization of parallel address generation units. Improvements and generalizations of previous work are described, and the e cacy of the proposed algorithms is demonstrated through experimental evaluation. 1Introduction & related work Design of embedded VLSI systems in form of heterogeneous single-chip architectures, comprising both hardware and software components, raises new demands on electronic CAD tools. Among the most challenging