Impact of Description Language, Abstraction Layer, and Value Representation on Simulation Performance

In recent years other verification features than simulation performance such as robustness and debugging gained increasing impact on simulation language and tool selection. However, fastest model execution speed is still priority number one for many design and verification engineers. This can be seen in the continuously growing interest in virtual prototypes and transaction level modeling (TLM). As part of the ongoing re-work modeling language strategies and the world wide introduction of TLM, a detailed analysis of the impact of description languages, abstraction layers and data types on simulation performance is of high importance. For the presented analysis, we considered five designs that have been modeled in VHDL, Verilog, SystemVerilog, and SystemC, using different value representations and coding styles, covering the abstraction levels from functional to behavioral to RTL. This paper presents our evaluation environment and several interesting findings of our analysis. The most important results are as follows: We found that HDL tool/language/abstraction selection of RTL models impacts on the execution speed with a factor of 4.4. We found that Verilog is on average 2times faster than VHDL for RTL models. We found that SystemC results in 10times slower RTL models than HDLs and surprisingly results in 2.6times slower TLM PV models than SystemVerilog. And we found finally that on average over all analyzed aspects SystemVerilog models are executed fastest