Chia-I Chen, Juinn-Dar Huang
Abstract
In this work, we thoroughly investigate all existing woks about distributed register-file micro architecture family with variant inter-island delay models, and the experimental results indicate that our work does provide better synthesis outcome than the prior art.
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In this work, we thoroughly investigate all existing woks about distributed register-file micro architecture family with variant inter-island delay models, and the experimental results indicate that our work does provide better synthesis outcome than the prior art.
Key concepts: Register file, Microarchitecture, Computer science, Register (sociolinguistics), Computer architecture, Architecture, Processor register, Parallel computing