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1983•Electronics LettersRequires access

Algorithm for VLSI chip floor plan

K. Ueda, H. Kitazawa

Open publisher page 6 citations

Abstract

An algorithm for a VLSI chip floor plan is presented. It uses initial block placement obtained by the AR (attractive and repulsive force) method, and performs iterative block packing by gradually moving and reshaping blocks with chip boundary shrinking. By the use of several types of experimental data, it is shown that the method is very effective for handling various types of blocks and is well suited to interactive chip layout design.

About this research paper

What this paper is about

An algorithm for a VLSI chip floor plan is presented. It uses initial block placement obtained by the AR (attractive and repulsive force) method, and performs iterative block packing by gradually moving and reshaping blocks with chip boundary shrinking. By the use of several types of experimental data, it is shown that the method is very effective for handling various types of blocks and is well suited to interactive chip layout design.

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OpenAlex reports 6 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

An algorithm for a VLSI chip floor plan is presented. It uses initial block placement obtained by the AR (attractive and repulsive force) method, and performs iterative block packing by gradually moving and reshaping blocks with chip boundary shrinking. By the use of several types of experimental data, it is shown that the method is very effective for handling various types of blocks and is well suited to interactive chip layout design.

Key concepts: Very-large-scale integration, Block (permutation group theory), Chip, Floor plan, Computer science, Boundary (topology), Plan (archaeology), Parallel computing

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